1. Field of Invention
The present invention relates generally to a method of fabricating a multi-chip module (MCM) package. More particularly, the present invention relates to a fabricating method of MCM package that can fabricate the substrate and the MCM package simultaneously.
2. Description of the Related Art
The demands of advanced electronic technology requires electronic products to be made lighter, thinner, faster and smarter while simultaneously making them more friendly, powerful, reliable, robust and less expensive. Therefore, the trend for electronic packages is to develop highly-integrated packaging structures. The multi-chip module (MCM) package can integrate several high performance chips together. Therefore, the packaging size is decreased and the reliability of the memory device is improved.
For a general multi-chip package, a plurality of bare dies or a portion of chips is packaged by using a surface mount technology (SMT) to integrated and connected to each other on a same substrate. The multi-chip package utilizes the bare dies to increase the package density, to reduce the required space and decrease the signal delay. Therefore, the multi-chip technique can achieve the high speed performance, and because several chips with various functions can be integrated together, thus, the multi-chip device has this advantage of consisting various functions.
The conventional method fabricating the MCM package is to adhere a plurality of chips onto the substrate first, then performing the packaging process. The method of adhering the chip to the substrate can be characterized into two types:
1. forming bumps on the chips to electrically connect the connecting pads of the substrate by utilizing the flip-chip packaging technique.
2. Using a wire bonding method to electrically connect the chip to the substrate (direct chip attach technique, DCA).
However, no matter what type of technique is used to connect the chip to the substrate, the patterned-traces and the patterns of the connecting pads on the substrate are defined for connecting to the chip. Several problems are induced by the conventional connection.
In general, a flux is applied to the connecting pads in a flip-chip type of connection. The chip is aligned to the connecting pads of the substrate first, and then a reflow process is carried out to bond the chip to the substrate. However, the reliability of the connection is undesirable and the input/output terminals of the chip are not always aligned to the connecting pads of the substrate. Further, if the connection has some problem, the rework is very difficult and complex.
A underfill process is required to fill a paste into between the chip and the substrate, the technique of this underfilling process is very complex and difficult. Air bubbles are easily produced during the underfilling, causing the yield of the product decreased.
For wire bonding process, the problems of the thin gold wires, the bonding strength of the wires, the connecting reliability can cause the electrical signal to delay. Further, a molding process is performed after the wire bonding process, air bubble may also produce during the molding process.
From the above-described conventional method of connecting the chip to the substrate, the connecting reliability is poor and the air bubble produced during the underfilling and molding processes to decrease the yield of the package.
It is an object of the present invention is to provide a method of fabricating a MCM package to improve the yield of the device. It is another object of the present invention to provide a method of fabricating a MCM package that can ensure the good connecting between the chip and the substrate. It is another object of the present invention to provide a method of fabricating a MCM package that can prevent the air bubble produced during the underfilling and molding processes.
To achieve the foregoing and other objects and in accordance with the purpose of the present invention, the present invention provides a substrate, and the substrate has an insulating core and a conductive layer. The conductive layer covers a bottom surface of the insulating core. A first opening is formed in the substrate to penetrate through the insulating core and the conductive layer. An adhesive tape is adhered on the substrate to cover a surface of the conductive layer, wherein the first opening exposes a portion of a top surface of the adhesive tape. A first chip is located on the exposed top surface of the adhesive tape, and the first chip has an active surface and a back surface. A plurality of bonding pads are formed on the active surface of the first chip, the back surface of the first chip is adhered onto the adhesive tape such that the first chip is located firmly on the adhesive tape. A patterned dielectric layer is formed to fill into the first opening such that a portion of the exposed top surface of the adhesive tape, the active surface of the first chip, the bonding pads of the chip and the insulating core are covered with the patterned dielectric layer. A plurality of second openings and third openings are formed in the patterned dielectric layer. The second openings expose the bonding pads of the first chip and the third openings penetrate through the patterned dielectric layer, the insulating core and the conductive layer. A metal layer is electroplated on sidewalls of the second openings and the third openings, and to cover the patterned dielectric layer. After the electroplating process, the adhesive tape is removed to expose the conductive layer, the back surface of the first chip and a portion of the patterned dielectric layer. A patterned metal and a patterned conductive layer are formed. A patterned solder mask layer is formed to cover surfaces of the patterned metal layer and the patterned conductive layer. A plurality of fourth openings and fifth openings are formed on the patterned solder mask layer to expose respectively a portion of the patterned metal layer and a portion of the patterned conductive layer. A solder ball process is carried out to form a plurality of solder balls on the fifth openings. A reflow process is carried out to electrically connect the solder balls to the patterned conductive layer. A second chip is electrically connected to the patterned metal layer via the fourth openings.
The present invention provides a method of fabricating a multi-chips module that can carry out the fabrications of the chip and the substrate simultaneously so that the flow of the fabricating process is simplified.
The present invention provides a method of forming the patterned dielectric layer in order to expose the bonding pads of the chip and then utilizing the electroplating method to form the metal layer so that the bonding pads of the chip is electrically connected to the substrate. Thus, the connection between the chip and the substrate is more reliable.
The present invention provides a method that can prevent the problem of the air bubble in the molding process or underfilling process.